De-Synchronisation: Asynchronous Circuits from Synchronous Specifications

Electronic Design Automation (EDA) is the most common approach for the fast design and implementation of large, complex ASICs and SOCs. We introduce an asynchronous EDA methodology that can be used to realize asynchronous circuits using conventional EDA tools and conventional technology libraries, starting from a synchronous synthesizable specification. It provides the key advantages of asynchronous implementation, low power and low EMI, at a reasonable cost in terms of area and performance, without requiring any change in the specification or in most of the flow. Our EDA flow is based on the concept of de-synchronization, whereby the clock distribution tree of a traditional synchronous circuit is replaced by a local synchronization mechanism, built out of very simple standard handshaking circuits. This idea has been discussed in various forms in the past; Research work by Linder followed up by Traver proposed to replace each gate (or combinational logic block in an FPGA-based implementation) of a synchronous circuit with a complex sequential circuit. Theseus Logic proposed a design flow that used synchronous tools for synthesis, and then replaced each combinational gate in the optimized circuit with a sequential majority-gate-based sub-circuit. However, both approaches result in a very high area and performance overhead, because they use a very small granularity. Our approach works at the level of combinational logic and multi-bit registers. Thus, as shown in the results section, it drastically reduces the overhead, while preserving the clock power and EMI advantages. Future work will address the other advantages of asynchronous circuits, namely low power by automated idling fine-grained clock gating, modularity, and average case performance. Our asynchronous EDA methodology was used successfully to implement four different versions of an asynchronous design, a DES encryption core. This gave us useful insights into the effectiveness of our approach.